Qualification and Failure Analysis


Presto Engineering’s Qualification Labs Bring Your New Product to Manufacturing Quickly and Reliably

Not only is Presto the right partner for designing your ASIC, we also have extensive experience in qualifying semiconductors, rooted with a long history in ASICs. With 50M€ of installed equipment in our 5 Test floors, our reliability services include all stresses necessary to qualify and release a new product to volume manufacturing. Our capabilities support die-, package-, and board-level qualification. Our talented experts are available to develop the most appropriate qualification plans for the mission profiles of your products. Our on-staff designers develop the custom hardware required for biased stresses. Additionally, in-house failure analysis lab will help your team root-cause any fall-out in record time.

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Complete HTOL/HAST Capabilities

One of the most complex stresses in a new product qualification is high/low temperature operating life (HTOL/LTOL - device qualification) and highly accelerated stress test (HAST - package qualification). Those stresses are biased (both require sockets and custom PCBs), long (typically 1,000-3,000 hours for HTOL) and often require complex electrical stimulations.

Presto Engineering will help develop and qualify appropriate electrical stimulations using our co-located testers and extensive test experience. We also support tester-based read-points with fast turn-around time.

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Custom Hardware Development

More often than not, a customer's ASIC is limited by the capabilities of the reliability chambers and capacity to handover test patterns/burn-in patterns from test production/characterization to reliability. Our ability to customize device reliability boards incorporating specific electronics to bridge the gap our customers need to stimulate their device and reflect the actual mission profile stress conditions.
We carefully select the right sockets and PCB technologies for the thermal (HTOL/HAST) and humidity (HAST) performances required.
Our ovens support sophisticated driver combinations in the chamber (hot) and outside (room). While standard systems max out at 100MHz clock speed, we leverage our RF experience into applications up to 2GHz. Our systems include chamber-controlled and socket-control temperature as well as custom systems (especially for RF applications) with device-controlled temperature.
Presto Engineering also supports full, in-situ monitoring of both electrical and thermal behavior.

Complete qualification solutions

Presto Engineering’s staff offers deep experience in silicon, III-V and photonics devices; they will support your product team with qualification plan development and report generation—in a format consistent with your market standards or end-customer requirement.

Additionnal Services

  • Reliability Risk Analysis (FMEA)
  • Qualification Plan / DOE
  • Board Design for Reliability (DfR)
  • Board Design for Analysis (DfA)
  • Destructive Physical Analysis (DPA)
  • Workmanship Evaluation
  • Projects for Technical Review/Audit
  • Reliability Result Analysis
  • Risk Analysis for New Revisions
  • Qualification Plan Update
  • Quality Issues: 8D, Audit, PDCA
  • Root Cause Analysis: 5 Whys Thinking or Apollo
  • Improvement Action Validation

Supported Stresses

  • Data Retention (DRET, JEDEC JESD22-A117)
  • HAST (JEDEC JESD22-A110, AEC Q100)
  • HTOL (JEDEC JESD22-A108, AEC Q100, IEC 60749-23)
  • HTSL (JEDEC JESD22-A103, AEC Q100, IEC 60068-2-1)
  • LTOL (JEDEC JESD22-A108, AEC Q100, IEC 60749-23)
  • LTSL (JEDEC JESD22-A103, AEC Q100, IEC 60068-2-2)
  • Preconditioning(JEDEC JESD22-A113, IPC/JEDEC J-STD-020, AEC Q100, IEC 60749-30)
  • Temperature Cycling(JEDEC JESD22-A104, AEC Q100, IEC 60068-2-14)
  • THB; 85/85 (JEDEC JESD22-A101, AEC Q100, IEC 60749-5)
  • UHAST(JEDEC JESD22-A118, AEC Q100)
  • Autoclave(JEDEC JESD22-A102, AEC Q100)
  • Mechanical Shock (JEDEC JESD22-B104)
  • Vibration (JEDEC, JESD22-B103)
  • Constant Acceleration(MIL-STD 883-2, M2001)
  • ESD Classification
  • LU Testing


Failure Analysis Capabilities

Presto Engineering offers a very wide range of failure analysis (FA) capabilities, for package-related failures, advanced CMOS, specialty semiconductor as well as subassembly level.

Our FA specialists address design debug, reliability-induced failures, as well as field return and RMAs. We use a well-established flow analysis framework that ensures fast turn-around time and consistency of results. Our FA teams leverage our in-house test floor to duplicate or screen incoming failing samples.

Failure Analysis examples


Trouble shooting

Wafer manufacturing issue.

A shift in top metal layer caused a MIM capacitor to short. Quick in-house trouble shooting saved an immense amount of time discussing with the fab.

Optimized development time

Optimized development time

An optimization in substrate design was considered due to noise. To evaluate if this was the right decision without waiting a long time for new substrates, a small part of the device was decapped, some wires removed, followed by glop-topping for protection. Subsequent test showed it to be a good solution and new substrate manufacturing was initiated.

Analyzing qualification samples

Analyzing qualification samples

Degradation of the lead-free solder joints with temperature cycling and effect of mechanical vibration testing was studied by cross sectioning the individual solder joints and evaluating their integrity, internal structure changes. Crack formations, solder grain structure changes, excessive IMC growth and nucleation of the micro voids into macro voids with time and testing were observed.

A Proven Development Proprietary Process

Presto Test Development flow is supported by our SquP (Service Quality Planning) proprietary process and OCEAN integrated web-based platform, making your project more predictable and reducing risk during development and ramp phases while providing both transparency and traceability.

Want to know how Presto can help you with your next project?