Developing a custom ASIC is complex but with the right approach and partners, it becomes a manageable journey from concept to finished chip.

If you are responsible for bringing innovative products to market, whether in medical devices, IoT, smart tracking, or other sectors, you have probably heard about the benefits of custom ASICs (Application-Specific Integrated Circuits).
ASICs can help reduce costs, shrink your product, and secure your supply chain. However, if you do not have a background in chip design, the idea of developing a custom ASIC can seem overwhelming.

ASIC Technology Is Mature. That Doesn't Mean It's Easy.

Custom ASICs are no longer reserved for billion-unit consumer products. From smart medical devices to industrial sensors and secure IoT platforms, application-specific chips offer unmatched performance, lower power consumption, and longer lifecycles.

Yet most original equipment manufacturers (OEMs) do not come from semiconductor backgrounds. Their teams understand their product, customers, and the market needs, but they may lack the knowledge to turn a block diagram into a chip.
When faced with a global supply chain, thousands of process steps, and tight time-to-market pressure, getting started can feel like a major risk.

But the truth is: you do not need to know how to build a chip. You need to know who to work with.

Where ASIC Projects Begin: It's About Outcomes, Not Schematics

ASIC development often begins with a vision, not a circuit. If you know what your product needs to do, and what challenges you are trying to solve, you are already at the starting line.

Start by asking yourself these key questions that will shape your ASIC development strategy:

• What functions do I want to integrate? This determines the chip's complexity and design requirements.

• What are the size, power, or regulatory constraints? These factors influence the choice of manufacturing process and design architecture.

• What are my expected volumes and product lifetime? This impacts cost calculations and manufacturing decisions.

• How will we test the chip at scale? Design for Test (DFT) strategies ensure defects are caught early, reducing post-production costs.

• Are there supply chain or obsolescence risks to manage? This helps determine the need for second-source options and long-term support planning.

The ASIC Development Journey – Explained

Here's a typical flow for ASIC development:

1. Feasibility Study

Every successful ASIC begins with a clear understanding of the end application. This stage includes analyzing multiple factors: technical requirements and constraints, resource availability and cost considerations, weighing the upfront investment against long-term unit cost savings. For a detailed analysis of ASIC economics and ROI, see our article on ASIC vs. Discrete Solutions.

This step involves:

• Architecture exploration: defining functional blocks, partitioning analog/digital elements, and estimating die size.

• IP selection: identifying reusable IPs or external IPs to license (e.g., ADCs, RF blocks, or embedded memories).

• Technology node evaluation: selecting a process technology based on performance, power, cost, and long-term availability.

• Packaging considerations: footprint, thermal requirements, and mechanical integration with the final product.

Making these decisions early helps reduce development time and cost, and aligns silicon capabilities with product expectations.

2. Specification and Test Strategy

Once feasibility is validated, detailed specifications are written to define the ASIC’s functional and electrical behavior:

• Logic and signal definitions

• Analog performance and sensor interfaces

• Timing, power consumption, temperature range, and reliability constraints

At this stage, a Design for Test (DfT) strategy is also defined. Defining DfT early ensures:

• Full test coverage (at wafer and package level),

• Optimized test time and cost,

• And robust production yield from first silicon through high volume.

3. Design & Prototyping

 In this stage, ASIC architects and layout engineers:

• Translate the specification into RTL and/or analog schematics

• Develop the digital logic, analog circuits, and mixed-signal interfaces

• Run full-chip simulations and verification, including corner cases

• Perform physical implementation: place & route, parasitic extraction, and timing signoff

• Run design rule checks (DRC), LVS, and formal verification

Tapeout is the milestone where the final layout is submitted to the foundry for mask generation. 

4. Manufacturing

Once tapeout is complete, the chip is fabricated, assembled, and tested: 

• Wafer fabrication: performed at the selected foundry, under process control

• Wafer testing (Wafer Sort): functional and parametric tests are run using test programs developed during the DfT phase

• Packaging: the good dies are assembled into selected package types (QFN, BGA, WLCSP, etc.)

• Package-level test: devices are re-tested post-assembly to validate performance and ensure no defects introduced in packaging

At this point, qualification testing (e.g., temperature cycling, HAST, ESD, MSL testing) is performed if required by the application (especially in medical, automotive, or industrial sectors).

5. Production & Delivery

Once the device is qualified, volume production begins, supported by test programs, logistics, and long-term planning.

• Volume production testing is optimized for throughput and cost, including yield monitoring and failure analysis if needed

• Traceability and lot control ensure full transparency, critical in regulated industries

• Long-term support: supply continuity planning (e.g., die banking, second sourcing, and packaging lifecycle management) is deployed

• Logistics: chips are delivered according to customer forecasts and requirements, with serialization and dry-pack options when needed

Each step involves its own complexity, tools, and risk. That's why companies often turn to an experienced ASIC partner who can handle the full journey—both technically and operationally.

Managing Complexity: The Role of an ASIC Partner

The development of an ASIC involves multiple disciplines and a highly specialized global supply chain—from design and prototyping to manufacturing, testing, packaging, and final delivery. For many OEMs, especially those without in-house semiconductor teams, managing this process alone is neither practical nor efficient.

A qualified ASIC partner can take ownership of the full development flow, including:

• Feasibility study 

• Circuit design and layout

• Test development (wafer-level and final test)

• Wafer sourcing and fabrication

• Packaging and assembly

• Component qualification and reliability testing

• Yield monitoring and long-term supply continuity

Historically, only large corporations maintained the internal teams and infrastructure necessary to manage these flows.

Today, fully integrated ASIC partners make custom chip development accessible to leaner organizations as well:
Reducing risk
Optimizing cost and timelines
Enabling faster market entry

Choosing the Right ASIC Partner

When selecting an ASIC partner, look for one with comprehensive capabilities and proven experience. For example, Presto Engineering supports OEMs in medical, industrial, and secure applications with turnkey ASIC development—from early feasibility to volume production.

Our strength lies in our ability to manage the entire ASIC lifecycle, combining:

• In-house test labs and qualification capabilities

• Proven silicon IP platforms to accelerate development and reduce cost

• Robust foundry and packaging ecosystems for scalable manufacturing

• Secure and traceable product development flow with myOCEAN, our proprietary web-based platform

  
  

➡️ Discover our ASIC Design Solutions and see how we help you turn your idea into silicon.