Our Reliability offering includes Soft Error Rate (SER) Testing, or SERTEST.
BACKGROUND Neutrons (landing on Earth from outer space) interfere with semiconductor devices and can create errors, from transient failures to severe latch-ups; such a phenomenon is measured as a Failure In Time (FIT). Semiconductor products must exhibit minimum FIT levels, in order to demonstrate adequate MTBF performance.
SER-induced FIT measurement procedures have been standardized by JEDEC with JESD 89 (2005 revision).
ACCELERATED TEST Like most reliability stresses, the objective is to accelerate a natural phenomenon in order to exhibit its potential damage--in a few days or weeks. Natural neutron emission (normalized as 12/cm2/hour in New York) would take sometimes months to exhibit an actionable failure. SERTEST is a specialized reliability test, using a high intensity neutron beam and alpha sources, that dramatically accelerates this process in order to produce FITs in hours or minutes.
SERTEST includes three phases:
SERTEST has been applied to SRAM and other memory products for years. With emerging 65nm and 45nm process technologies, SERTEST becomes a requirement for Flip-Fops, FPGAs and now ASICs/SOCs. Additionally, Soft Error Testing emerges as a central requirement not only for communication and servers, but for automotive, mobile and medical applications.
Please call us at 408-434-1808 x303 or contact us and schedule a discovery meeting to understand how Presto Engineering will provide you with the value of state-of-the-art test and failure analysis—at a cost your business can afford.
Exclusive NAM provider
