Most interactions with chips (outside the fab) are performed through outside leads, or pins, and with electrical signals (driven or measured). When situations arise whereby electrical behaviour cannot be explained from these outside signals, product engineers need to go 'inside' the device to understand physical behaviours.

A critical step in that determination is to find out where to look. Any corrective action recommendation will require a physical view down to the gate level. With tens of millions of gates within few square millimiters, this is the well-known 'needle in a haystack' challenge.

The techniques highlighted below are used for such localisation.

These techniques can be grouped in four categories:

• Legacy techniques (LC, FMI), fairly routinely used in the past (and still today on large features); their limited resolution make them marginally useful for modern process technology.
• Front-side techniques (PEM and OBIRCH) were first used with advanced optics, supporting sub-micron resolution; however, with most common defects buried in lower levels, their usability diminished past 4-5 metal layers processes.
• Back-side techniques (infra-red) allowed better access to buried defects that manifest themselves statically (typically fab-related random defects).
• Dynamic back-side techniques are now the state-of-the-art in physical fault isolation, as they enable detection of systematic, design-related defects that only manifest themselves when execised with ATE.

Presto Engineering specializes in all these techniques, with a special emphasis on dynamic back-side fault isolation.